The present invention relates to accessing pattern memory in automatic test equipment ("ATE") testers for testing electronic circuits, and more particularly to accessing pattern memory in systems using a processor-per-pin architecture. One such system is described in commonly-owned U.S. Pat. No. 5,212,443.
In a processor-per-pin architecture, a tester has local sequencers, each of which is programmable to provide events to a pin of a device under test (a "DUT"). In a system of this kind, each local sequencer generates events with reference to a global clock and other global signals. Characteristically, each local sequencer is individually programmable so that different sequencers can provide different events during the same test period. Characteristically, too, each local sequencer has a memory for storing events and a separate, local memory for storing test vectors.
Testers commonly provide 1 or 2 bits of pattern data for each pin in each vector, and one vector in each test period. A tester may provide test vectors having a depth of 4 bits or more. The actual data storage component of local memory is commonly a set of dynamic random access memory (DRAM) devices or synchronous DRAM devices, whose high average data rate is subject to interruption by required refresh cycles and setup times. It is therefore advantageous to provide pattern data from local memory through a FIFO (first-in, first-out) structure, such as the one described in commonly-owned U.S. Pat. No. 5,122,988, the disclosure of which is incorporated herein by this reference.
To accommodate the ever-increasing size and complexity of integrated circuit devices, automatic test equipment must achieve increasing flexibility of operation. The present invention is directed to apparatus and methods that increase the flexibility of methods by which pattern data may be accessed while a tester is running a functional test.